1. Field of the Invention
Embodiments of the invention generally relate to integrated circuit packaging structures.
2. Background of the Related Art
Microelectronic devices typically include one or more die (i.e., micro integrated circuits formed on a single substrate) having a multitude of die bond pads, a chip body, and an interconnection scheme to connect the pads on the die to a supporting substrate. Generally, the supporting substrate is formed into a package around the die to provide physical protection from contaminates. The combination of these is generally referred to as a xe2x80x9cchip packagexe2x80x9d. According to conventional packaging methodologies, the number of interconnects for common integrated circuit (IC) packages such as a dual-inline package (DIP), single-inline package (SIP), and others, is limited to the perimeter of the package. Generally, a ball grid array (BGA) package style is used to facilitate an increased connection density. The BGA package provides interconnections from the package bottom or top surface, thus increasing the number of potential interconnection points.
Generally, the ICs increase in speed and performance is directly coupled to an increased device operating frequency. Unfortunately, the increase in device frequency often in the giga-hertz range increases the device sensitivity to parasitic capacitance and inductance. The device packaging, die, and internal die interconnections provide for potential frequency issues. For example, to decrease the height and cost of packaging, device packages are often molded simultaneously to a plurality of individual IC circuits on one substrate. Subsequently, the individual circuits are then cut away from the single substrate using, for example, a high-speed saw to form individual ICs. Unfortunately, as device frequencies increase the type of packaging material used to protect the circuits from external damage and contamination decreases the overall IC performance. To accommodate the higher IC performance, IC manufacturers often use individual ceramic covers having a lower dielectric constant in lieu of the molded package. Unfortunately, to add individual covers is expensive relative to the molded packaging and therefore is often avoided, thereby sacrificing IC performance in devices such as cellular phones. Further, while the individual covers often provide increased device performance, the process of applying the covers often damages the ICs they are designed to protect, thereby decreasing IC throughput and increasing IC cost.
Therefore, what is a needed is a method and apparatus to provide an efficient and a cost effective package for integrated circuits.
Embodiments of the invention provide a method, article of manufacture, and apparatus for providing component packages for components such as integrated circuits. In one embodiment, the invention provides a method of packaging at least one component, comprising forming a component package assembly including a plurality of component packages on a carrier where each of the plurality of component packages includes a cavity to receive the at least one component therein, and then separating the component packages into a plurality of individually packaged components.
In another embodiment, the invention provides a method of packaging at least one component, comprising forming a body including a plurality of separable component packages on a carrier, and forming a cavity within each of the component packages to enclose the at least one component disposed on the carrier therein.
In another embodiment, the invention provides an apparatus for enclosing at least one component, comprising a component package assembly including a plurality of separable sidewalls formed on a carrier wherein the separable sidewalls and carrier define a plurality of separable component packages adapted to enclose the at least one component therein.